1. Field of the Invention
The present invention relates generally to Bi-CMOS logic circuits comprising a bipolar transistor and an insulated gate type field effect transistor, and more particularly, to an improvement of a Bi-CMOS logic circuit structured with Bi-CMOS technique, that is, hybrid integration technique of integrating a bipolar transistor and an insulated gate type field effect transistor on the same substrate.
2. Description of the Background Art
In recent years, in order to effectively utilize low power consumption of an insulated gate type field effect transistor (referred to as MOS transistor hereinafter) and large current drivability and high speed operation of a bipolar transistor, a function circuit is formed by integrating a MOS transistor and a bipolar transistor on the same semiconductor substrate. A function circuit obtained by such a hybrid integration technique is referred to as a Bi-MOS circuit. Particularly, when comprising both a P channel MOS transistor and an n channel MOS transistor, it is referred to as a Bi-CMOS circuit.
FIG. 1 shows one example of a conventional Bi-CMOS logic circuit. The Bi-CMOS logic circuit shown in FIG. 1 is a three-input NAND circuit, and which is disclosed, for example, in Patent Laying Open No. 61-54712.
Referring to FIG. 1, the Bi-CMOS logic circuit comprises a first NPN bipolar transistor Q1 and a second NPN bipolar transistor Q2 for driving an output V0. A collector of the fist bipolar transistor Q1 is coupled to receive a first power supply V.sub.CC, and an emitter thereof is connected to the output V0. P channel MOS transistors (referred to as PMOS transistor hereinafter) MP1, MP2 and MP3 are connected in parallel between the collector and a base of the bipolar transistor Q1. Gates of the PMOS transistors MP1, MP2 and MP3 are coupled to inputs VI1, VI2 and VI3, respectively. N channel MOS transistors (referred to as NMOS transistor hereinafter) MN1, MN2 and MN3 are connected in series between the base of the bipolar transistor Q1 and a second power supply V.sub.EE. Gates of the NMOS transistors MN1, MN2 and MN3 are connected to the inputs VI1, VI2 and VI3, respectively.
The second bipolar transistor Q2 for driving an output has its collector connected to the output V0 and its emitter connected to the power supply V.sub.EE. NMOS transistors MN4, MN5 and MN6 are connected in series between the collector and a base of the bipolar transistor Q2. An NMOS transistor MN7 is connected between the base and an emitter of the bipolar transistor Q2. Gates of the NMOS transistors MN4, MN5 and MN6 are connected to the inputs VI1, VI2 and VI3, respectively. A gate of the NMOS transistor MN7 is connected to the base of the bipolar transistor Q1. Now, an operation thereof will be described.
When at least one of the inputs VI1-VI3 is at the "L" (logical low) level, the output V0 rises to the "H" (logical high) level. At this time, at least one of the MP1-MP3 is turned on, while at least one of the NMOS transistors MN1-MN3 is turned off, whereby the base of the bipolar transistor Q1 is coupled to the power supply V.sub.CC through a PMOS transistor in on state. As a result, the base potential of the bipolar transistor Q1 rises, so that the transistor Q1 is turned on.
On the other hand, under this condition, at least one of the NMOS transistors MN4-MN6 is turned off, and the NMOS transistor MN7 is turned on in response to the rise of the base potential of the bipolar transistor Q1. Accordingly, a base potential of the bipolar transistor Q2 is discharged through the NMOS transistor MN7 in on state, so that the bipolar transistor Q2 is turned off. As a result, the output V0 is charged through the bipolar transistor Q1, so that the output V0 rises to the "H" level.
When all of the inputs VI1-VI3 are at the "H" level, the output V0 falls to the "L" level. In this state, all of the PMOS transistors MP1-MP3 are turned off, and all of the NMOS transistors MN1-MN3 are turned on. As a result, the base potential of the bipolar transistor Q1 is discharged through the NMOS transistors MN1-MN3 to fall, so that the bipolar transistor Q1 is turned off. On the other hand, all of the NMOS transistors MN4-MN6 are turned on, and the NMOS transistor MN7 is turned off in response to the fall of the base potential of the bipolar transistor Q1. Accordingly, the base potential of the bipolar transistor Q2 rises by the charging from the output V0, so that the bipolar transistor Q2 is turned on. As a result, the output V0 is discharged through the bipolar transistor Q2, so that its potential falls.
In a structure of a conventional Bi-CMOS logic circuit, since the gates of the NMOS transistors MN1-MN3 for drawing out base charge of the bipolar transistor Q1 are connected to respective input terminals, an input capacitance is increased so that a load to a driving circuit in a preceding stage is increased. When the input capacitance is thus increased, much time is required to establish an output of the driving circuit (input of a Bi-CMOS logic circuit), thereby making a logical operation at a high speed impossible. In addition, in order to drive such a large input capacitance at a high speed, the driving circuit has to be made large in scale.
In case of such a multi-input logic circuit as shown in FIG. 1, a plurality of transistors are needed for drawing out base charge of the bipolar transistor Q1, so that the number of component elements and a layout area are increased, which prevents high integration. In order to remove a drawback of such a logic circuit, a structure is proposed in which the number of components and an input capacitance are reduced.
FIG. 2 shows a structure of another conventional Bi-CMOS logic circuit. The Bi-CMOS logic circuit shown in FIG. 2 is a three-input NAND circuit, which is disclosed in Japanese Patent Laying-Open No. 63-240125. In FIG. 2, the same reference numerals are allotted to the corresponding portions to those in the circuit structure shown in FIG. 1. In a circuit structure of FIG. 2, an NMOS transistor MN8 is disposed between the base of the bipolar transistor Q1 for driving an output and the second power supply V.sub.EE. A gate of the NMOS transistor MN8 is connected to the base of the second bipolar transistor Q2 for driving an output. More specifically, a single NMOS transistor MN8 is employed for drawing out a base charge of the bipolar transistor Q1. Now, the operation thereof will be described.
In a structure shown in FIG. 2 as well, the output V0 rises from the "L" level to the "H" level, if at least one of the inputs VI1-VI3 is at the "L" level. In this state, at least one of the PMOS transistors MP1-MP3 is turned on. Before a potential of the output V0 rises, a base potential of the bipolar transistor Q1 is approximately at the "L" level, and the NMOS transistor MN7 is turned off and a base potential of the bipolar transistor Q2 is approximately the same as that of the output V0. Thus, the NMOS transistor MN8 is turned off. Subsequently, the base of the bipolar transistor Q1 is coupled to receive the power supply V.sub.CC through a PMOS transistor in on state, so that the potential thereat rises and the bipolar transistor Q1 is turned on, whereby the output V0 is charged from the power supply V.sub.CC.
At this time, since at least one of the NMOS transistors MN4-MN6 is turned off when the base potential of the bipolar transistor Q1 rises, the NMOS transistor MN7 is turned on correspondingly. Thereby, the base potential of the bipolar transistor Q2 is discharged through the NMOS transistor MN7 in on state, so that the bipolar transistor Q2 is turned off. As a result, the output V0 is charged by the bipolar transistor Q1 to rise to the "H" level.
The output V0 falls from the "H" level to the "L" level, when all of the inputs VI1-VI3 are set at the "H" level. At this time, all of the PMOS transistors MP1-MP3 are turned off, while all of the NMOS transistors MN4-MN6 are turned on. As a result, the base potential of the bipolar transistor Q2 is charged from the output V0 through the NMOS transistors MN4-MN6 in on state, causing the base potential of the bipolar transistor Q2 to rise. Thus, the NMOS transistor MN8 is turned on to fall the base potential of the bipolar transistor Q1, so that the transistor Q1 is turned off. On the other hand, the NMOS transistor MN7 is turned off in response to both the rise of the base potential of the bipolar transistor Q2 and the fall of the base potential of the bipolar transistor Q1. As a result, the output V0 is discharged through the bipolar transistor Q2 in on state to fall to the "L" level.
In a structure of the above described another conventional Bi-CMOS logic circuit, only a single NMOS transistor MN8 is provided as a transistor for sinking out base charge of the bipolar transistor Q1, and the circuit may reduce an input capacitance, the number of elements and a layout area.
However, when the output VO falls in that circuit, the base potential of the bipolar transistor Q2 becomes lower than the output VO by the amount of on-resistances of the NMOS transistors MN4-MN6, and the NMOS transistor MN8 can not be deeply turned on. Therefore, it requires much time for the base potential of the bipolar transistor Q1 to fall, which delays turn off of the bipolar transistor Q1 and NMOS transistor MN7. As a result, the switching speed of the circuit is reduced.
In addition, when the bipolar transistor Q1 is delayed in turn off, the output VO falls slowly. If the output VO falls slowly (i.e. the falling time period thereof becomes longer), the base potential of the bipolar transistor Q2 falls slowly and a time period when the bipolar transistor Q1 and the bipolar transistor Q2 are simultaneously turned on becomes longer. In this case, a current flows from the power supply V.sub.CC to the another power supply V.sub.EE, so that a power consumption is increased. The reduction of the switching speed and the increase of the power consumption are especially acute when the threshold voltage V.sub.th of the NMOS transistors is larger and the power supply voltage V.sub.EE is smaller.
Other structures of a Bi-CMOS logic gate circuit are disclosed in Japanese Patent Laying-Open No. 61-20426. This prior art reference discloses a logic gate circuit comprising a P channel MOS transistor having a source connected to a base of an NPN bipolar transistor for charging an output terminal, a drain connected to the output terminal, and a gate connected to an emitter of the NPN bipolar transistor for discharging the output.